\doxysection{FMC\+\_\+\+Bank1\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_f_m_c___bank1___type_def}{}\label{struct_f_m_c___bank1___type_def}\index{FMC\_Bank1\_TypeDef@{FMC\_Bank1\_TypeDef}}


Flexible Memory Controller.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank1___type_def_a161ea3265a8e17e5c7ef12f7ea19ff52}{BTCR}} \mbox{[}8\mbox{]}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Flexible Memory Controller. 

\label{doc-variable-members}
\Hypertarget{struct_f_m_c___bank1___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_f_m_c___bank1___type_def_a161ea3265a8e17e5c7ef12f7ea19ff52}\index{FMC\_Bank1\_TypeDef@{FMC\_Bank1\_TypeDef}!BTCR@{BTCR}}
\index{BTCR@{BTCR}!FMC\_Bank1\_TypeDef@{FMC\_Bank1\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BTCR}{BTCR}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank1___type_def_a161ea3265a8e17e5c7ef12f7ea19ff52} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank1\+\_\+\+Type\+Def\+::\+BTCR\mbox{[}8\mbox{]}}

NOR/\+PSRAM chip-\/select control register(\+BCR) and chip-\/select timing register(\+BTR), Address offset\+: 0x00-\/1C 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
